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[SOLVED] Scan Chain Insertion with DFT

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sampham04

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Hi,

I inserted a scan chain into a circuit using Synopsys DC then simulated it through Tetramax, but only got a fault coverage of 6.67%. I'm not exactly sure what the problem is, but I think it might have something to do with the way my scan chain was inserted.

The code I am trying to insert a scan chain into is:
module dff(CK, Q, D);
input CK, D;
output Q;
reg Q;

always@(posedge CK)
Q <= D;
endmodule

module s27(GND,VDD,CK,G0,G1,G17,G2,G3);
input GND,VDD,CK,G0,G1,G2,G3;
output G17;

wire G5,G10,G6,G11,G7,G13,G14,G8,G15,G12,G16,G9;

dff DFF_0(CK,G5,G10);
dff DFF_1(CK,G6,G11);
dff DFF_2(CK,G7,G13);
not NOT_0(G14,G0);
not NOT_1(G17,G11);
and AND2_0(G8,G14,G6);
or OR2_0(G15,G12,G8);
or OR2_1(G16,G3,G8);
nand NAND2_0(G9,G16,G15);
nor NOR2_0(G10,G14,G11);
nor NOR2_1(G11,G5,G9);
nor NOR2_2(G12,G1,G7);
nor NOR2_3(G13,G2,G12);

endmodule

And the steps I used to create the scan insertion are:
set_scan_configuration -style multiplexed_flip_flop
compile -scan
set_dft_signal -view existing_dft -type ScanClock -port CK timing[list 40 60]
create_test_protocol
dft_drc
set_scan_configureation -chain_count 1
preview_dft
insert_dft
write -format verilog -hierarchy -output s27_dft.v
write_test_protocol -out s27_dut.spf

After that I don't get any errors, but I do get this warning:
The multi-clock protocol requires that the strobe time be before a clock's pulse if it is used for transition fault testing. (TESTXG-56)

Do you have any ideas of something I should change or add in order to increase my fault coverage to an acceptable amount?

Any suggestions you have would be much appreciated.

Thank you!
 

sampham04

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In Tetramax after reading in the library and the DFF.v and s27_dft.v files

run_build_model s27
run_drc s27_dut.spf
set_patterns -random
add_faults -all
run_simulation
set_simulation
run_fault_sim
 

kornukhin

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The multi-clock protocol requires that the strobe time be before a clock's pulse if it is used for transition fault testing. (TESTXG-56)

To remove warning change your ScanClock timing from {40 60} to {>40 60}. Because 40 - is default value for "test_default_strobe". You can get current value for this variable using "echo $test_default_strobe".
Or you can change value for "test_default_strobe" and left ScanClock timing {40 60}.

Using TetraMax I got 71,15% coverage (with your script). Your value can be little different depends on your std cell library (by the way you needn't read DFF.v inside TMAX)
 

sampham04

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Is there a way to get Tetramax to print out the input values used during fault simulation along with the flip flop and output values that are associated with each input pattern?
 
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kornukhin

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You can write test pattern, and get verilog testbench. Using it you can see all i/o patterns.
 

sampham04

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I used the command write_patterns patterns.v but when I open the file all I get is this:
^@^@^@^V^@^@^@ÿÿÿÿÿÿÿÿ^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^@^F^@^@^@^D^@^@^@^@^@^@^@^@^@^@T^A^@^@^@^D^@^@^@^A^@^@^@^@@jf^C^@^@^@^D^@^@^@^B^@^@^@^@^@^@P^E^@^@^@^D^@^@^@^C^@^@^@^B^@^@^@^G^@^@^@^D^@^@^@^D^@^@^@^@^@^@d ^@^@^@^B^@^@^@

I tried write_patterns patterns.v -format verilog, but it said that -format verilog was obsolete so the command was ignored.

Also, how would I create the testbench? Would I need to use VCS to run the test bench after it's written?
 
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kornukhin

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I used following command:
write patterns tb.v -format verilog_single_file -replace -serial
After all you can simulate tb.v using VCS (or another simulator). For VCS script looks like this:
vcs -v stdlib.v -v iolib.v -v net.v tb.v -timescale=1ns/100ps -o test_dft -debug_all
./test_dft -gui
Both VCS and TetraMAX 2010 releases.
 

sampham04

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I tried -format verilog_single_file but it still says that the command is ignored because it is obsolete. So I'm trying to simulate the pattern file generated without the -format verilog option, but when I type in the script you provided it says that both the stdlib.v and iolib.v library files cannot be opened because they do not exist. Do you know which directory it should be in so that I can check to see if it is there?
 

kornukhin

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Read TetraMAX User Guide for right syntax of the "write pattern" for your version of TMAX.

In VCS script stdlib.v and iolib.v are just example libraries. Use "yourlibrary".v instead.
net.v is netlist
tb.v - testbench from TMAX
 

sampham04

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So, I've found that I can only write the pattern file in binary, VHDL, STIL, and a few other things, but no verilog. If I were to write the pattern in VHDL would there be a way to use both my verilog design file and the VHDL test bench in VCS together?
 

kornukhin

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VCS supports Verilog/VHDL/SystemVerilog... I've never made VHDL/Verilog simulation using VCS, so I can't share script right now.

TMAX doesn't support verilog? What version of TetraMAX do you use?
 

sampham04

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I have version E-2010.12-SP4. It also says that in the next version that comes out the VHDL option is going to become obsolete too.

Do you have a script for simulating VHDL files? I was thinking I could have the Design Compiler insert the scan using VHDL instead of Verilog and then I wouldn't have to do a simulation mixing Verilog and VHDL.
 
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kornukhin

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I don't have VHDL script. Maybe I will make it in a week.
I just used TetraMAX D-2010.03-SP4 for generation test patterns.
1. start tmax shell using "tmax -nogui -notcl"
2. write_patterns tb.v -verilog_single_file -serial
Everything works fine.
 

sampham04

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Ok well I'll keep looking for ways to either mix the simulation or do it all in VHDL. Thank you so much for all your help!
 

tys

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Hi, it looks TetraMAX 2010.03 and previous versions support the verilog testbench. But the versions after that do not support verilog testbench (neither table nor single file), regardless of the parameter "-nogui" or "-notcl".
And i guess it is due to the ltran, a third-party software...

so, i also want to know, how do you produce verilog testbenchs with latest TetraMax versions, please?
or what kind of procedure do you use to produce the TetraMax pattern/testbech for simulation?
thanks.
 

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