[SOLVED] Sawtooth Wave Generator (1.5V to 14.5V)

[silentscream4]

Hello!
I wanted to generate a Sawtooth wave! whose lower peak should be from 1.5V and higher peak should be till 14.5V and frequency should be 100Hz!

Can anyone suggest a circuit?

Thanks in Advance!

 

[BradtheRad]

What likely prospects have you examined thus far?

 

[sreekanthr.ele]

Please find the below

Sometimes it is felt necessary to provide a relatively slow linear ramp with a rapid fall (or rise in the case of a negative ramp) at its end. This is a sawtooth wave. Also, in applications such as time base generators and power control circuits, the sawtooth must be triggered by (or be synchronized with) some control signal.



sawtooth waveform
The difference between the triangular and sawtooth waveforms is that in triangular waves the rise time is always equal to its fall time while the sawtooth waveforms have different rise and fall times i.e. sawtooth wave may rise positively many times faster than it falls negatively or vice-versa.

The circuit shown in figure provides the ability of controlling ramp generation with an external signal. In the circuit shown, an NPN BJT has been placed around the charging capacitor C and emitter of the transistor is tied to the inverting (-) terminal of the op-amp, which is at virtual ground. Resistor RB is for limiting the base current and so for protecting the BJT. However, RB is to be kept rela*tively small to assure that the transistor can be driven into saturation.

With a zero or negative control input voltage, the transistor is off. The capacitor charges up from the op-amp output, through C, Rin and to V-. The charge rate is given as

Rate = V- / Rin *C

If the control voltage is not changed, the capacitor C will eventually charge up, and hold the output at + Vsat.

However, when a positive control input is applied, the transistor gets turned on. If this voltage is large enough to force transistor into satu*ration the capacitor is effectively short- circuited. The capacitor C rapidly dis*charges.

The output voltage falls to zero (actually about 0.2 V) and stays there as long as positive control voltage keeps the transistor saturated. The expected obtainable waveform is given in figure. For control of negative going ramps, the circuit shown in figure will require several minor changes. First, the charging voltage, connected to Rin, polarity will have to be reversed to V+. This reverses the direction of charging current. It means capacitor will also have to reversed, if it is electrolytic one. The emitter of the transistor must be connected to virtual ground (the inverting input terminal of op-amp). To allow the capacitor to discharge from left to right, NPN transistor would have to be replaced by PNP transistor. In this case, a zero or positive control input would keep the PNP transistor off, while a negative control input would be required to turn the transistor on.