Saturated CMOS Inverter problem.

[cannibol_90]

Saturated NMOS Inverter problem.

Hi,

I was trying to simulate a nMOS saturated inverter in AWR AO.



1. The bias voltage in the attached figure is 5V. But the inverter gives an output of 2.5V. In contrast, a CMOS inverter gives an output voltage of 5V. Why is it that so?



2. As Gate and Source are shorted, the upper nMOS is is always in saturation. If the output voltage is fixed at 2.5V, does it mean that the threshold voltage of the upper nMos is 2.5V?

Vds = Vgs - Vt

Vds = -Vt ( As Vg = Vs)

By KVL (Vdd to ground) : Vds = 2.5

Hence Vt = -2.5V??? (for nMOS???)


HELP???

- - - Updated - - -

Also I need to know whether a CMOS inverter gives more or less propagation delay than an ordinary NOT Gate.

 

[erikl]

Re: Saturated NMOS Inverter problem.

1. The bias voltage in the attached figure is 5V. But the inverter gives an output of 2.5V. In contrast, a CMOS inverter gives an output voltage of 5V. Why is it that so?

See item 2

2. As Gate and Source are shorted, the upper nMOS is is always in saturation. If the output voltage is fixed at 2.5V, does it mean that the threshold voltage of the upper nMos is 2.5V?

Vds = Vgs - Vt

No: Vds = Vgs = Vt + Vod ; Vod = Voverdrive is the voltage additional to Vt , which is necessary to allow for the Ids current of the upper side NFET, which is sunk by the lower side NFET.

By KVL (Vdd to ground) : Vds = 2.5 ; Hence Vt = -2.5V??? (for nMOS???)

No: Vds = Vt + Vod , so Vt could be +1V and Vod = +1.5V .

Also I need to know whether a CMOS inverter gives more or less propagation delay than an ordinary NOT Gate.

Prop. delay for output falling should be about the same (depends mainly on the W/L ratio of the lower side NFET). For rising output, prop. delay of the NMOS inverter will be longer than for a CMOS NOT gate, because the "diode connected" upper side NFET usually provides less current than a full power supply controlled PMOS with same W/L ratio.