[SOLVED] Sate assignment VHDL versus Verilog

I have a question about implementing an FSM in Verilog. In VHDL, we assign states using a type:

type state is (s1,s2,s3);

the only way I can see to do something like this in verilog is with parameters:

parameter s1=2'b00, s2=2'b01, s3=2'b10;

this implementation seems very lacking to me for couple reasons. If I go back and add more states, I could end up needing more bits. I could end up needing to modify the declaration of 128 states to add number 129, etc.

More importantly, optimal state assignment is not a trivial problem. Different state assignments can have significant impact on power, area and speed of a design. In the VHDL case, the synthesizer can assign the states according to an optimization algorithm, whereas when I write the code, states are just going to be added in the order I think of them, practically guaranteeing a sub-optimal assignment.

Sorry for the long lead-in. My basic question is:
How do I write a verilog FSM that allows the compiler to assign states? I'm using synplify, if anyone is aware of a compiler directive for this.

Matthew

the only way I can see to do something like this in verilog is with parameters

Click to expand...

It's Verilog.

More importantly, optimal state assignment is not a trivial problem. Different state assignments can have significant impact on power, area and speed of a design. In the VHDL case, the synthesizer can assign the states according to an optimization algorithm, whereas when I write the code, states are just going to be added in the order I think of them, practically guaranteeing a sub-optimal assignment.

Click to expand...

Fortunately, most synthesis tools will simply ignore your hand coded enumeration and code state variables according to their default FSM coding style (mostly one hot), unless you explicitely specified a particular style through synthesis attributes or another means. But I'm not aware how it's handled in Synplify, you should check the user's manual.

Lets use example at this link
The case statement at that link can be modified to use parameters
// Declare parameters soon after Inputs/Outputs declaration
parameter S1 = 10, S2= 11,S3 = 12, S4= 13, S5 = 14, S6= 15;
// Replace the values with parameters
case (r_count)
S1 : begin
packet_in = 'haa; wr_en = 'b1; end
S2 : begin
packet_in = 'hbb; wr_en = 'b1; end
S3 : begin
packet_in = 'hcc; wr_en = 'b1; end
S4 : begin
packet_in = 'hdd; wr_en = 'b1; end
S5: begin
packet_in = 'hee; wr_en = 'b1; end
S6 : begin
packet_in = 'hff; wr_en = 'b1; end
default: begin
packet_in = 'd0; wr_en = 'd0; end
endcase end

Note Referred the example from fullchipdesign.com/verilogtb.htm

Wow, I didn't expect a response so quickly. Thanks, FvM! That answered my question. The idea of hand-coding state values just seemed ludicrous. It's still annoying to have to assign a number to each state that will just be ignored anyways, but as you said, It's verilog. I'm going to mark this as solved.

atulaxc, thanks for taking the time to respond. Your answer didn't really address my question though. I know about using parameters, I wanted a way to do an FSM without explicit assignments.

Matthew