Continue to Site

Welcome to

Welcome to our site! is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

SAR ADC, Input driving op-amp and its output RC filter.

Not open for further replies.


Advanced Member level 2
Dec 6, 2013
Reaction score
Trophy points
Activity points
Hello to you all.

I am going to use my first SAR ADC and I'm not sure if I should put this in the analog section or if its an appropriate topic for this part or not but please move it if it was wrong choice.

To the subject at hand, I have a ADC that has a input small-signal-bandwidth of 4MHz while only being able to output 200kSPS max. Apparently this allows it to capture high frequency transitions or transients through under-sampling which I need to read up on but that means that the op amp I need has to have >4MHz small-signal-bandwidth.

I have read a few pdf's about this subject but I can't extract any useful info through me failing to grasp what the are trying to convey with all equations and all.

The conversion time is 5µS for 200kSPS(4,8MHz SCLK 24clockCycles/conversion), I don't really know what data you/I need to tell but how do I derive suitable values for R and C to be put on the converter input to isolate the amplifier from the ADC?
And I guess anti-aliasing is a second purpose.

The acquisition time can be calculated as tACQ = 13(RS + RIN) x 35pF where: RIN = 800Ω and RS is the source resistance which needs to be below 1kΩ to not effect the ADC performance.

The application is for DC voltages but with a point to also reveal information about ripple voltage in the 20kHz range and also 50Hz/100Hz ripple if that would be present. I don't know quite what to aspect, there might not be any ripple for the ADC to handle but I want to allow for the design to process that kind of frequency's. Actually I want to allow for as much high frequency content as possible to be captured as long as that does not degrade the DC performance which is in the end the main application. The input capacitance of the ADC is typically 40pF.


First of all, why do you want to "isolate the amplifier from the ADC"?

Generally, manufacturers will have recommended driver opamps, as well as typical application circuits. Even if your BW is low, the fast switching of the input capacitors on the ADC require a faster opamp than you might think. But I'm SURE there's some manufacturer recommendations and application information in the data sheet.
  • Like
Reactions: David_


    Points: 2
    Helpful Answer Positive Rating

some SAR ADCs have interal amplifier. They are much easier to drive. ..

But we talk about ADCs without amplifier.
They usually have a "hold" capacitor. The built in "sample and hold" circuit connects the hold capacitor to the output only during "sample" phase.

Within the time of the sample pahse the capacitor needs to be charged - best to an error of less than 1 LSB.
If you have an input resistor then it builds an RC circuit with the internal hold capacitor.

For a 200kSmpl/s ADC maybe the sample time is 1us. With a 16 bit ADC one LSB = 0.00001526 of fullscale.
Within one RC constant the capacitor is charged with 37% error = 0.37.
for two RC the error is 0.37 x 0.37 = 0.137;
for 3 RC--> 0.051
and so on..
you need more than 11 RC (fixed value for 16 bit ADCs) to charge to an error of less than 0.00001526
the mathematical calcualtion is: log(0.000015)/log(0.37) = 11.2

now you know 11 RC are 1us. then you can calculate that one RC = 91ns.

Maybe the charge capacitor C = 6pF. then you can calculate "R". R = 91ns / 6pF = 15kOhms.

This means you should not use source resistor of more than 15kOhms. With no additional C.

An external RC can be used as antialiasing filter, and/or to improve OPAMP driver stability.
For an antialiasing: then usually the external capacitor is much larger than the internal, so the internal capacitor gives no relevant error.

For stability reasons: You need an OPAMP that can drive low ohmic loads and should stabilize much faster than the "sample" time of the ADC. Often you find a value of xx nanoseconds to 99% of target value.
This is 1% error or 0.01. But you want 0.000015 within 1us. log(0.000015)/log(0.01) = 2.4 ; 2.4 times xx ns = 1us --> xx = 414ns,
You need to find an OPAMP that is able to react on a step input with less than 414ns to 99% of the end value.
(But this is for worst case... the error step won´t be 100% full scale for example...)

You will soon find out that a 741 won´t do this. Then better first try without an OPAMP, if you are not satisfied with the result you may add an OPAMP - check if it improves accuracy.

A lot of good OPAMP can drive 600 Ohms loads without instability. If you now take the 91ns RC of the calcualtions above you get a max. C of 151pF (worst case)
In reality a 1nF capacitor may be a good choice.

Much calcualtions....
But as said before it is "worst case" when you want to go to the limit.

Relax! With your application you are far away...

Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to