SAR ADC Clock Generation

[Monady]

Hi,

I was looking at several theses on SAR ADC and could not find a way to generate required clock signals for sampling the input signal, resetting capacitor and comparator, ....
Assuming we have only one clock signal for the SAR ADC and we want to generate all required clock pulses internally, how one can generate them and with which circuit? I appreciate if someone suggests me a thesis or a good paper about it.

 

[crutschow]

They make many crystal oscillator modules that will generate the desired clock frequency. Why no use one of those?

 

[Monady]

They make many crystal oscillator modules that will generate the desired clock frequency. Why no use one of those?

Hey. Sorry I didn't get what you mean. How crystal can help?
Basically my question is that assume having only one master clock, how and with what circuit one can generate all other clock signals required for the SAR ADC, including clock for the input sampling, resetting capacitors, and resetting comparator, ...

 

[erikl]

... generate required clock signals for sampling the input signal, resetting capacitor and comparator, ....

Assuming we have only one clock signal for the SAR ADC and we want to generate all required clock pulses internally, how one can generate them and with which circuit? I appreciate if someone suggests me a thesis or a good paper about it.

To generate the clock signals for sampling the input signal, resetting capacitor and comparator, you just need a non-overlapping two-phase clock generator, which is controlled by your a.m. clock signal. (First of all, this is not unique for an SAR ADC, but for any ADC with sampled input).

To clock the individual n-bit SARegisters, you need an n-bit counter with decoded output, e.g. an n-bit feedback shift register.

Re. literature: search for non-overlapping two-phase clock generators, or e.g. Andrew Masami Abo's thesis Design for Reliability of Low-voltage, Switched-capacitor Circuits, p. 105 (p. 119 of the PDF).

 

[dick_freebird]

Each stage (SAR, DAC, comparator, S/H) has its own timing
and these need to be sequenced for best sampling rate and
accuracy tradeoff. A small state machine with either higher
speed clocking, or self-timed, is likely what you want. The
analog elements' settling time, response time will set the
timing requirements and you need to map all of that out.

 

[Monady]

To generate the clock signals for sampling the input signal, resetting capacitor and comparator, you just need a non-overlapping two-phase clock generator, which is controlled by your a.m. clock signal. (First of all, this is not unique for an SAR ADC, but for any ADC with sampled input).

To clock the individual n-bit SARegisters, you need an n-bit counter with decoded output, e.g. an n-bit feedback shift register.
.

Hey, thanks for the description. I guess I should have explained my question more clearly, sorry about that. Assume you want to design a 10-bit SAR ADC with 1MSPS output. So the internal clock would be 12 MHz, I have attached a picture from a thesis showing required clocks for a 10-bit SAR ADC.

in this picture you see that the one on top is the main clock (12 MHz) provided from outside, the second one is the delayed version of that. The third one is for shorting the output of the preamplifier, the forth one is for auto-zeroing, the fifth one is for sampling input on the capacitors, ...
I am mostly interested in a circuit that generates the clocks mentioned above from a single master clock. Non-overlapping clock generator will not generate those signals, and the counter and shift register you mentioned above are for controlling switches connected to the DAC. I could not find a digital circuit in theses talking about generating those signals.

- - - Updated - - -

EA small state machine with either higher
speed clocking, or self-timed, is likely what you want.

Hi, would you please let me know if there is any paper or thesis designing a circuit for that?

 

[erikl]

... Assume you want to design a 10-bit SAR ADC with 1MSPS output. So the internal clock would be 12 MHz, I have attached a picture from a thesis showing required clocks for a 10-bit SAR ADC.

in this picture you see that the one on top is the main clock (12 MHz) provided from outside, the second one is the delayed version of that. The third one is for shorting the output of the preamplifier, the forth one is for auto-zeroing, the fifth one is for sampling input on the capacitors, ...
I am mostly interested in a circuit that generates the clocks mentioned above from a single master clock.

So this 10-bit SAR ADC has its own special clocking structure, I see. As you know the timing of all the required clock signals, you can derive all of them from the main clock: the delayed version either by a simple gate delay - if you don't need high precision - or a DLL circuit (self_timed) or a PLL circuit (higher speed clocking). Now you've got all the necessary edges to build the other clock signals.

All this circuitry together is what dick_freebird calls the state machine, I think.