there is a timer that is clocked by clock_S
while someone sends a 1 cycle strobe at clock freq X
need to supply a valid value of timer after maximum 4 X clocks from strobe
cdc should be kept
now if clock S is fast no problem, strobe X can be synced to domain Sand it meets the
4 X clocks
ok, still suppose timer S runs at 100 Mhz (10ns)
while clock X runs at 500 M (2ns)
when there is a strobe X, application must get the timer value up to 4 X cycles (8 ns)
thats less than S clock period
so problem seems to be solved by sampling the timer every 10 ns at S domain
but the transfer to domain X is hard (need prevent cdc problems)
how do we know when is the last valid sample just before strobe X etc
seems easy when thinking but dont find the formulation
Clock X is fast enough to perform synchronous edge detection of clock S. The synchronized clock S allows to sample timer S safely at clock domain X. So it's continuously available.
Alternatively, a gray coded count value can be transferred safely without synchronization. That's the usual method to exchange pointers in domain crossing FIFOs and even works, if both clock domains have almost same frequency.
The above seems to assume there will be no metastability on the registers in edge_det. It probably needs extra registers for the counter and the clock_S, so the edge detection can be reliably done, and the counter can be the correct value associated with the delayed clock edge.
I think the gray codes are probably a better choice overall.
Yes, at least for the dege detection. With a 4:1 frequency ratio, the below code still works. If the double registering of clock_S achieved in edge_det[1] doesn't give sufficient metastability margin, I would prefer gray encoding.
Code:
edge_det[2:0] <= {edge_det[1:0],clock_S};
if (edge_det[2:1] == '01')