Sampling a multibit signal at clock domain crossing

[abhinavpr]

Hi,

i have to sample a 16bit data bus at 50 MHz into a 300 Mhz domain.

as the reading is faster than writing, should i use a FIFO for this? what would be the FIFO depth?
or should i simply sample the data bus every 6 clk cycles in 300 MHz domain and use 16 2-stage synchronizer on each bit of the data bus?

is there any other efficient way of doing it?


-abhinavpr

 

[KlausST]

Hi,

Is the 50MHz clock synchronous to the 300MHz clock.
If yes: then you could wirk with 1/6 clock sample.
If no: then you need a flag that shows when new data is valid.

But i recommend in both cases a flag to avoid reading data at exactely the time when data changes.

Klaus

 

[abhinavpr]

thnks for your reply.

i came across MUX-D synchrozing technique for multibit clock domain crossing.
is it a recommended design practise?

in mux-d synchronizer only a control signal indicating change in data is synchronized and the data is sampled at this point.
i have attached the diagram for it.

will it hold any benifit over FIFO?

In my opinion we will have to generate control signal to indicate data change in a similar way we generate write enable for FIFO, but i think with FIFO we will have more freedom whether to read data as it is comming or wait for say 10 data to be written(50 MHz) and then read (300 MHz) 10 data in 10 consecutive clk cycles?

am i thinking in right direction?

 

[KlausST]

HI,

in my eyes the most important question is:

Is the 50MHz clock synchronous to the 300MHz clock.

Klaus