sample data at rising/falling edge of clock?

[ilikebbs]

If receiver samples data at falling edge of clock, transmitter will send data on falling edge or rising edge clock?

I know that it is recommend to use the same edge clock in FPGA design.
But which edge should be used for data transmission between chips?
thanks.

 

[laktronics]

Hi,
If the receiver and transmitter use the same clock and if the transmitter outputs the data synchronised with the rising edge, then the data is assured to be available and stable at the falling edge, so that it is better that the receiver uses the falling edge to strobe the data.

Regards,
Laktronics