[SOLVED] Sample Code VHDL SDRAM burst mode read to BRAM in Nexys 2

[Harish Naman]

Hi, I want to obtain a 128 word burst transfer of data from SDRAM to BRAM in Nexys 2 board. I have gone throught the nexys 2 reference manual and sample code given at their product page. But that is asynchronous mode read. I want to obtain a burst mode transfer.
Also i want to know about the burst transfer to the BRAM from the SDRAM. I am not able to find any sample code related to that. I have also gone through the Micron Datasheet, I could understand what has to be activated and what has to be sent...but i am confused with so much of information. Kindly help me by providing some sample code for Burst Transfer from SDRAM to BRAM.

Please find Links for
1. Digilent Nexys 2 Board http://www.digilentinc.com/Products/Detail.cfm?Prod=NEXYS2
2. Micron SDRAM datasheet http://download.micron.com/pdf/datasheets/psram/128mb_burst_cr1_5_p26z.pdf

Thanks in Advance

 

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Well you need a SDRAM controller that supports 128 word burst transfers. Giving links to the Nexys 2 and the SDRAM datasheet doesn't help supply you with what you need. Open the Xilinx Coregenerator and select the MIG and generate a core. If the SDRAM controller core from Xilinx doesn't support burst transfers you'll a) have to modify the core so it does, b) buy a different core that supports that feature, or c) write your own SDRAM controller core.

 

[Harish Naman]

Xillinx core generator supports only DDR SDRAM. It doesn't support the memory which is present in my board. Can you tell me the step by step procedure to write own SDRAM Controller Core.

Well you need a SDRAM controller that supports 128 word burst transfers. Giving links to the Nexys 2 and the SDRAM datasheet doesn't help supply you with what you need. Open the Xilinx Coregenerator and select the MIG and generate a core. If the SDRAM controller core from Xilinx doesn't support burst transfers you'll a) have to modify the core so it does, b) buy a different core that supports that feature, or c) write your own SDRAM controller core.

 

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Xillinx core generator supports only DDR SDRAM. It doesn't support the memory which is present in my board. Can you tell me the step by step procedure to write own SDRAM Controller Core.

1. Read the SDRAM datasheet.
2. Design a circuit that meets the timing requirements of the SDRAM device and produces the correct protocol for interfacing to the device.
3. Code it in your HDL of choice.
4. Simulate the code in a simulator, and fix anything that violates the SDRAM specification.

This is like design engineering 101. If you're not a hobbyist or a first/second year engineering student I'd seriously consider a career change.