sample and hold without latch infered

hulk789 · Jul 28, 2015

Code:

always @ (sample,inp) begin
         if(sample==0 ) begin
             vinp=vinp;
         end
         else begin
             vinp=inp;
         end
    end

is it possible to not infer a latch for a sample and hold type of code in synthesis.

TrickyDicky · Jul 28, 2015

No. Anything that has memory will infer a latch.

K-J · Jul 28, 2015

hulk789 said:
is it possible to not infer a latch for a sample and hold type of code in synthesis.

Yes, a flip flop.

Kevin Jennings

- - - Updated - - -

TrickyDicky said:
No. Anything that has memory will infer a latch.

You know better than that. Flip flops are memory and they are not a latch (in the context of what a designer would describe and use, not what a flip flop is at the transistor level).

Kevin

FvM · Jul 28, 2015

Anything that has memory will infer a latch.

Should be read "A memory in combinational always block". I guess.

There are some applications where you intentionally infer a latch, e.g. in some cases, a transparent latch is better suited as address register in a multiplexed processor bus than a flip-flop.

ads-ee · Jul 28, 2015

And the code specified by the OP is a latch

Code Verilog - [expand]
1
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3
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5
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8
always @ (sample,inp) begin // combinational code as FvM mentioned
         if(sample==0 ) begin
             vinp=vinp;  // memory as Tricky mentions
         end
         else begin
             vinp=inp;
         end
    end

Without a posedge or negedge sensitivity on a signal the always block will always infer either combinational logic or a latch (if any outputs are fed back or not defined in a branch).

K-J · Jul 28, 2015

ads-ee said:
And the code specified by the OP is a latch

Yes the OP posted code for a latch, but the question the OP posted is can you not infer a latch for a sample and hold. The answer there is yes, use a flip flop.

Kevin

sample and hold without latch infered

hulk789

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Code Verilog - [expand]
1 2 3 4 5 6 7 8	always @ (sample,inp) begin // combinational code as FvM mentioned if(sample==0 ) begin vinp=vinp; // memory as Tricky mentions end else begin vinp=inp; end end

sample and hold without latch infered

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