Apr 3, 2008 #1 O oskar11 Newbie level 4 Joined Feb 19, 2008 Messages 5 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,314 can anybody help me about the sample and hold structure for the first stage of pipeline adc. (It will sample 10Ms/s.)
can anybody help me about the sample and hold structure for the first stage of pipeline adc. (It will sample 10Ms/s.)
Apr 4, 2008 #2 L ljy4468 Full Member level 4 Joined Jul 20, 2005 Messages 232 Helped 13 Reputation 26 Reaction score 1 Trophy points 1,298 Location South Korea Activity points 3,023 You can use Switched-capacitor type with non-overlapping clock for up to 13~4bit resolution.(two stage opamp or gain booster) For more resolution, you can use gate-bootstrapping technique. There are many helpful thing in S.Lee 's thesis.
You can use Switched-capacitor type with non-overlapping clock for up to 13~4bit resolution.(two stage opamp or gain booster) For more resolution, you can use gate-bootstrapping technique. There are many helpful thing in S.Lee 's thesis.
Apr 6, 2008 #3 U userss Newbie level 4 Joined Mar 18, 2008 Messages 6 Helped 1 Reputation 2 Reaction score 0 Trophy points 1,281 Activity points 1,312 can you upload Lee's thesis or give a link??