sample and hold for pipeline

[oskar11]

can anybody help me about the sample and hold structure for the first stage of pipeline adc. (It will sample 10Ms/s.)

 

[ljy4468]

You can use Switched-capacitor type with non-overlapping clock for up to 13~4bit resolution.(two stage opamp or gain booster)
For more resolution, you can use gate-bootstrapping technique.
There are many helpful thing in S.Lee 's thesis.

 

[userss]

can you upload Lee's thesis or give a link??