"some_package_1" contains a constant named : "some_constant"
Code:
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
package body some_package_1 is
constant some_constant : std_logic := '0' ;
end package body some_package_1 ;
"some_package_2" contains a constant with the same name but a different value.
Code:
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
package body some_package_2 is
constant some_constant : std_logic := '1' ;
end package body some_package_2 ;
In my code, I'd like to compare "some_constant" from some_package_1 to "some_constant" from some_package_2.
Code:
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
library work ;
use work.some_package_1.all ;
use work.some_package_2.all ;
.
.
.
signal some_signal : std_logic ;
begin
some_signal <= some_constant(from some_package_1) and some_constant(from some_package_2) ; -- How should I rewrite this line to make it work?
end architecture ;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
library work ;
-- use work.some_package_1.all ; remove this
-- use work.some_package_2.all ; and this
.
.
.
some_signal <= work.some_package_1.some_constant and work.some_package_2.some_constant ; -- change here
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
library work ;
--use work.some_package_1.all ;
--use work.some_package_2.all ;
entity some_entity is
end entity some_entity ;
architecture rtl_some_entity of some_entity is
signal some_signal : std_logic ;
begin
some_signal <= work.some_package_1.some_constant and work.some_package_2.some_constant ;
end architecture ;
As suggested these have been commented away
--use work.some_package_1.all ;
--use work.some_package_2.all ;
Compilation fails.
I found the bug.
This code compiles now without errors (even with the ".all" in place).
Code:
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
library work ;
use work.some_package_1.all ;
use work.some_package_2.all ;
entity some_entity is
end entity some_entity ;
architecture rtl_some_entity of some_entity is
signal some_signal : std_logic ;
begin
some_signal <= work.some_package_1.some_constant and work.some_package_2.some_constant ;
end architecture ;
The problem was in the packages.
I declared the constants in the package body instead of in the package head.
I.E, I changed this:
Code:
library ieee ;
use ieee.std_logic_1164.all ;
package some_package_1 is
end package some_package_1 ;
package body some_package_1 is
[B]constant some_constant : std_logic := '0' ;[/B]
end package body some_package_1 ;
To this:
Code:
package some_package_1 is
[B]constant some_constant : std_logic := '0' ;[/B]
end package some_package_1 ;
package body some_package_1 is
end package body some_package_1 ;
Did the same change for "some_package_2" and now it compiles.
The constants are not exported because they are not contained in the declaration. A package body isn't needed at all for constant definition. Try this way
But FvM was pointing out that you kept the package body, which is now empty - this is not required.
Overall this is a scoping problem, and again, as pointed out, only things in the package declaration are visible externally. Declaring new items in the body are only visible in the body, and dont need a corresponding declaration in package declaration region.
Another thing that has always been possible in packages is deferred constants. This way you can declare the constant without a value in the package declaration, and then assgn the value in the body. This could allow you to have multiple values for constants by have multiple bodies in different files, and only compiling the one needed in the given project.
This has become somewhat redundant in VHDL 2008 with the inclusion of package generics (and in VHDL 2017 generics specifically on protected types too )