library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity final is
port( clk_in_for_fixed,clk_in_for_programmable,xor_in_1,xor_in_2,not1_in1,not2_in2: in std_logic;
clk_out_fixed, clk_out_programmable,xor_out,not1_out,not2_out: out std_logic;
programmable_divide_value : in std_logic_vector (9 downto 0)
);
end final;
architecture Behavioral of final is
signal counter_fixed,counter_programmable,fixed_divide_value,programmable_divide_value : integer := 0;
begin
fixed_divide <= 40;
programmable_divide <= to_integer(unsigned(programmable_divide_value(9 downto 0)));
process(clk_in_for_programmable)
begin
if( rising_edge(clk_in_for_fixed) ) then
if(counter_fixed < fixed_divide/2-1,) then
counter_fixed <= counter_fixed + 1;
fixed_clk_out <= '0';
elsif(counter < fixed_divide-1) then
counter <= counter + 1;
fixed_clk_out <= '1';
else
fixed_clk_out <= '0';
counter_fixed <= 0;
end if;
end if;
end process;
if( rising_edge (clk_in_for_programmable) then
if(counter_programmable< programmable_divide/2-1) then
counter_programmable <= counter_programmable+ 1;
clk_out _programmable<= '0';
elsif(counter_programmable< programmable_divide-1) then
counter_programmable <= counter_programmable+ 1;
clk_out _programmable<= '1';
else
clk_out_programmable_<= '0';
counter_programmable_ <= 0;
end if;
end if;
end process;
end Behavioral;