rules of thumb in setting up constraints

[rntsay]

i'm trying to setup these constraints in design compiler
are there general rules of thumb on how to define T1,...,T6?
i figure that all will be some fraction of the clock period....
but what's a "typical" setting if there is such a thing?

set_clock_uncertainty -setup $T1 MyClock

set_clock_uncertainty -hold $T2 MyClock

set_input_delay -min $T3 -clock MyClock [all_inputs]

set_input_delay -max $T4 -clock MyClock [all_inputs]

set_output_delay -min $T5 -clock MyClock [all_outputs]

set_output_delay -max $T6 -clock MyClock [all_outputs]

 

[bala_EE]

I dont know if there are any rules of thumb. Because for example, the clock uncertainity provides a margin or an estimate of the setup and hold times that have to considered while synthesizing the design. So my opinion is that there are no hard and fast rules. Please clarify if I am wrong.

 

[soloktanjung]

Hello,

I also want to know how do we decide the constraints values for the commands above. Do we estimate randomly? I trying to constraints my design but don't know what is the realistic values?

Yes I know it depend on a design, but what is the basis for us to put that values? I read from my course notes that we can use the values from place and route steps, but how, I mean using what command for example in SOC Encounter?

Can anyone please shows me?

Thanks.