[SOLVED] RTL errors while portling simulation tools

[dpaul]

Hi all,

I would like to keep it simple & would provide details as needed by expanding the thread.

Background: There is an existing legacy uP RTL code which simulates perfectly well with VCS Synopsys. Now I need to use that legacy code to simulate the uP core using ModelSim (it is impossible for me to use VCS, I don't have access to it).

RTL language is Verilog + SystemVerilog

While simulating in ModelSim I am getting error messages.

How do I go about solving this problem?

Thanks.

 

[barry]

Um, maybe read the error messages? Don't they tell you what the problem is?

I realize you don't want to provide too much detail, but you don't provide ANY!!

What kind of errors? Multiple drivers? Missing library? Segment fault? Your question is a bit too vague.

 

[dpaul]

Sorry for that, I want to give out the details as needed so as to avoid confusion.

I get the following error message from many module level *.sv design files.
** Error: (vsim-3906) : Enum types must match.

Why is this not reported by VCS for other users?
I am should be using legacy code and not supposed to change the RTL files. But now these simulation time errors are limiting me.
I am using ModelSim SE-64 10.2b for simu using the -novopt switch.

 

[FvM]

Is it asking too much that you examplarily track down the error message to the related code, at least in a single case?

 

[ads-ee]

Are you enabling the -sv switch in modelsim?

 

[dpaul]

ok, so now I am using Synopsys VCS-MX and none of the errors appears!

Just for information to others:
VCS passed where ISIM(Vivado) and ModelSim had both failed.

This leads me to the conclusion that all SV constructs are not handled by all tools.