the AE from Cadence told me that the design synthesized by their synthesis tool RTL Encounter(RC) is much smaller than by DC(2004.06), and saves much run time. but i am not sure. did anybody here compare the two tools with your own design ?
it's true, the same case as synplify vs fpga compiler, but, the dc is the industrial standard now, it's the only problem to replace it with other asic synthesis tools.
I think RTL Complier is very powerful. It also includes the Physical Complier's function of Synopsys.
But it is very expensive. Certainly, DC is the familiar tool for most designer.
the AE from Cadence told me that the design synthesized by their synthesis tool RTL Encounter(RC) is much smaller than by DC(2004.06), and saves much run time. but i am not sure. did anybody here compare the two tools with your own design ?
The results from SNUG are also confusing, it not easy to make clear which is better, but it seems that get2chip's product works well, at least i know that there are some drawbacks with DC
However, with DW and data-path optimization, DC can process more complex design and get better
results than RC.
But for non-accurate wire-load model, the result will get worsen after place.
DC + PC + Astro is most powerful flow.
Thus need run DC with new configuration with old flow.