RTL and constraints for DFT normal and scan clocks

Hello
I am new to DFT and I want some help with the following long issue
A design has 3 clocks A, B and C with frequencies 100MHz, 50MHz and 20MHz respectively. All clocks are asynchronous from different clock sources. All three clocks are used in the block. Paths between clocks can be considered false paths for now
We need to have one DFT scan chain with Clock A as the scan clock. For the blocks that are clocked by B and C should be clocked by A when in scan mode.
When in scan mode, clock_A will be low frequency like 20MHz or 30MHz not 100MHz

My problem is how to properly write the RTL and constraints for the block

I think I needed to write the following RTL
assign clock_B_s = (scan_mode) ? clock_A : clock_B;
assign clock_C_s = (scan_mode) ? clock_A : clock_C;
where clock_B_s and clock_C_s will clock regions B and C respectively.

For constraints, I wrote "create_clock" for A, B and C with their corresponding periods. My questions now are:
do I have to write constraints for "clock_B_s" and "clock_C_s" using "create_clock" or "clock_generated_clock"?
do I have to tell the tool that clock_B_s and clock_C_s are asynchronous?
if there is another clock that is inverted from clock_A, what constraints should I apply on it ?
ex assign clock_A_inv = (scan_mode) ? ~clock_A : clock_A;
Should I do something else that I missed above?

Thank you