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Rth measuring condition ("PCB is verticall in still air")

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Feb 13, 2022
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Good morning everybody.

I am working on the estimation of Rth junction-TopCase for power transistors. For this purpose, I need the thermal information provided by the manufacturer. I mainly work with Infineon who always gives the same comment in their datasheets:

"Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain connection. PCB is vertical in still air."

I know JEDEC (JESD51-2A) gives some guidelines about how to characterize devices but it is always in horizontal position. Not vertical.

What brings Infineon to do it vertically? if so, I have not found any information about the setup they used. Any suggestion?

Some bibliography:

Infineon Power Transistor Example

Cooling concepts for CanPAKTM package

Thermal Resistance - Theory and Practice

Gallery of Photos:


You'll expect slightly lower Rth with vertical board orientation due to increased natural convection. The actual value depends on total board dimensions and many other parameters.

These JEDEC and datasheet board examples are attempts to define a reference setup, not practical calculation guidances. Real boards rarely consist of just one transistor mounted similar to the reference setup. For real design, use state-of-the-art thermal simulations tools or determine Rth empirically.

I understand that, and probably they use this approach for getting a lower Rth value compared to other competitors.

I have already used some FEM simulation tools as ANSYS for this purspose however I would like to develope a method for estimating Rth Junction-Top Case only by using datasheet information (In the ones that it is not provided). For this purpose, it is important to replicate the exact test bench they used for getting those Rth values.

Do you think this test bench even exists or it is only guessed trough simulation?. I mean this because in page 22 of:

Thermal Resistance - Theory and Practice

They seem to extract Rthja value only trough ANSYS simulation.

Thank you.

Board size and orientation are expected to affect Rja (junction-ambient), but should not significantly affect Rjc top or Rjc bottom (usually this is called Rjb), since those paths exist only inside the device packaging.

But I wonder why you're interested in the top side Rjc for such a package. That datasheet shows it will be a factor of 10 greater than Rjb, so it probably won't contribute much even if you attach a heat spreader.

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