Routing vs. Logic percentage estimation in an FPGA design

[msdarvishi]

Hello everyone,

I was wondering if there is a way to estimate the routing vs. logic percentage utilized in an implemented design into FPGA after PAR?? Is it possible to do it with Xilinx tools? I would like to mention that I am using Xilinx ISE 14.7 with XC5VLX50T (Virtex-5) FPGA.

Thanks and Regards,

 

[TrickyDicky]

Afaik, unless you have some logic that have some rediculous fan outs all close to each other, routing resource is going to be difficult to predict. Its hard enough to predict logic usage (ram and dsp usage is rather easy).

If you're getting problems with routing, you might want to start duplicating some signals.