In other words i haven't any oscillator for my module and i want to use the oscillator that is on the FPGA board.
I assume from your approach the only reasonable way to get at the oscillator is
through the fpga? Anyways, like permute said, the warnings are because of delays. If you want to get rid of those you can add an entry to your .UCF file.
Code:
# UCF entry to Timing IGnore the XClk signal, to prevent those pesky warnings
NET "XClk" TIG;
Add that in your ucf and you should get rid of the warning. Might even change the routing a little, it depends. But since you're familiar with fpga editor that's easy to check.
The simulator giving X's sounds more like an initialization error in the testbench... Did you give the Clk register in the testbench an initial value?
Either way, if you haven't fixed it yet, for the X's problem best to post the testbench + a screenshot of the signal with the X's...
---------- Post added at 17:27 ---------- Previous post was at 17:09 ----------
Also, a DDR output register like this really isn't hard. If you ever have hand instantiated an IOB FF, then you have already done the "hard" part. The only difference is 2 data inputs and 2 clock inputs. And IIRC spartan-3 doesn't have local clock inversion, so that would mean having to go through a DCM to get clk_0 and clk_180.
All in all, if you don't have data going out then just do what you were already doing. Only real problem as far as I can tell is fix the testbench...
Code:
reg ClkIn; // I am assuming you have something like this in the testbench
initial begin
ClkIn = 0; // If so, don't forget to initialize it like this...
end
// generate clock
always begin
#100 ClkIn <= ~ClkIn;
end
Anyways, something like that... Hope that helps.