promach
Advanced Member level 4
May I know why 'priority' signal is fed back to AND gate input ?
What is the purpose of the AND gate in the picture below ?
From googling, I found this article , but I am not sure if the AND gate in the article serves the similar purpose.
The article implementation uses some mask vector which seems a bit strange and complicated in terms of hardware resources as well.
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I just got an answer from one of my friend:
What is the purpose of the AND gate in the picture below ?
From googling, I found this article , but I am not sure if the AND gate in the article serves the similar purpose.
The article implementation uses some mask vector which seems a bit strange and complicated in terms of hardware resources as well.
- - - Updated - - -
I just got an answer from one of my friend:
priority' signal is fed back so that the given priority stays on for multiple cycles since the registers are not conditionally clocked
So, if priority 1 is high and all the grant inputs are low, it will stay high forever.
Well, better wording would be: it is looped back into the AND gate for the purpose of it staying on forever and the AND gate is there to cut it off in case a grant input becomes high
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