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| // arbiter logic
module arbiter(clk,rst,req,gnt);
input clk,rst;
input [3:0]req;
wire [3:0]out0;
wire [3:0]out1;
wire [3:0]out2;
wire [3:0]out3;
output [3:0]gnt;
reg [3:0]outs;
wire [3:0]en;
rc r0(.clock(clk),.reset(rst),.q(en));
prlogic p0(.req(req),.out(out0),.en(en[0]));
prlogic p1(.req(req),.out(out1),.en(en[1]));
prlogic p2(.req(req),.out(out2),.en(en[2]));
prlogic p3(.req(req),.out(out3),.en(en[3]));
or a0(gnt[0],out0[0],out1[0],out2[0],out3[0]);
or a1(gnt[1],out0[1],out1[1],out2[1],out3[1]);
or a2(gnt[2],out0[2],out1[2],out2[2],out3[2]);
or a3(gnt[3],out0[3],out1[3],out2[3],out3[3]);
endmodule
// ring counter logic
module rc (clock,reset,q);
input clock,reset;
output [3:0] q;
reg[3:0] q;
always @(posedge clock)
if (reset)
q <= 4'b0001;
else
begin
q <= q<<1;
q[0]<=q[3];
end
endmodule
// priority logic
module prlogic(req,en,out);
input [3:0]req;
input en;
output [3:0]out;
wire [1:0]x;
encoder4_2 e0( .din(req) ,.dout(x),.en(en) );
decoder2_4 d0( .a(x),.v(out),.en(en) );
endmodule
// priority encoder logic
module encoder4_2 ( din ,dout,en );
output [1:0] dout ;
reg [1:0] dout ;
input [3:0] din ;
wire [3:0] din ;
input en;
always @ (din or en)
begin
if(en==1 | din==4'b0001 | din==4'b0011 | din==4'b0111 | din==4'b1111)
dout=2'b00;
else if(en==1 | din==4'b0010 | din==4'b0110 | din==4'b1110)
dout=2'b01;
else if(en==1 | din==4'b0100 | din==4'b1100)
dout=2'b10;
else if(en==1 | din==4'b1000 )
dout=2'b11;
else
dout=2'bz;
end
endmodule
// decoder logic
module decoder2_4 ( a ,v,en );
output reg [3:0]v;
input [1:0]a ;
input en;
always @(a or en)
if(en)
begin
v[0] <= (~a[0]) & (~a[1]);
v[1] <= (~a[0]) & a[1];
v[2] <= a[0] & (~a[1]);
v[3] <= a[0] & a[1];
end
else
begin
v[0] <= 1'bz;
v[1]<= 1'bz;
v[2]<= 1'bz;
v[3] <= 1'bz;
end
endmodule |