Rom inference in Verilog

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amolgupta87

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I have a logic function to implement. It's quite an odd/irregular one and large. I have a truth table to represent it. In order to implement it i would like to have a constant array having. How can I have an array in verilog which also gets synthesized(what construct / keyword). The value of array will not change.

P.S. my synthesis tool is rc from cadence.
 

Am not sure try this
Declare 2d array

assign a[0] = 5'd1;
assign a[1] = 5'd2;

since we are driving the constant, i felt that tool may infer this as ROM.
 

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