Rising edge of IN- maintains value of 1 how?

[vishal_sonam]

Hello. I have a query.
Suppose we have only 1 signal i.e., IN and it is on rising edge as I have understood rising edge mean mean TRUE means from 0 to 1 and then it will go down from 1 to 0 so for a very short time it will be maintained as 1.(0 to 1 then 1 to 1 and then 1 to 0) My question is how it will be maintained as 1 ?What is reason behind that?
I hope I mentioned my query well and hope you all have understood it
Thanks

 

[sharath666]

That is because such circuits are edge triggered; in this case rising edge triggered.
The main motivation behind using a clock is precisely control the timing of events. In this circuit every event will happen only at the rising edge of the clock. So at the first rising edge the signal will go from a 0 to a 1. It will continue to be 1 till the next rising edge. At the next rising edge, the signal goes back to 0.
I hope I have understood and answered ur question.

 

[std_match]

My question is how it will be maintained as 1 ?What is reason behind that?
Thanks

No, the rising_edge will not be maintained as "true". It will only be "true" for one time step in the simulation. The "rising_edge" is an event, it can not be maintained.

 

[ads-ee]

Hello. I have a query.
Suppose we have only 1 signal i.e., IN and it is on rising edge as I have understood rising edge mean mean TRUE means from 0 to 1 and then it will go down from 1 to 0 so for a very short time it will be maintained as 1.(0 to 1 then 1 to 1 and then 1 to 0) My question is how it will be maintained as 1 ?What is reason behind that?
I hope I mentioned my query well and hope you all have understood it
Thanks

Your question in this thread and in your previous thread are vague. You should instead describe what you are trying to accomplish. You need to say what kind of signal IN is.
e.g. IN is a well behaved pulse (i.e. Not from a mechanical button press) of X ns duration that has to be captured and occurs at an interval of Y ns.
You don't seem to be approaching this from a hardware perspective (i.e. a method should be called on a rising edge of IN and on every change of RESET). VHDL isn't an object oriented programming language, it's a hardware description language. A flip-flop is uses a rising edge signal called the clock to change state and it's not a method it's a piece of hardware. I've already shown you how to describe a flip-flop in your other thread.

Now if this rising edge stuff you keep getting stuck on is because you want to DETECT the rising edge of a pulse. Then there are a number of ways to approach this.
A couple of options come to mind.
1. Over sample the IN signal with a clock that has a period that is at least 1/3rd to 1/4th the pulse width to synchronize it to the clock and then detect the leading edge of the pulse.
2. Use a toggle flip-flop and use the IN signal as the clock input. Synchronize the toggle output and run that through an edge detector (using an XOR instead of an AND).