hello, i designed an edge detector in verilog. it's RTL seems correct, but in simulation the output pulse is delayed. The examples on the internet, the pulse starts exactly with the rising edge of the clock signal. i used no delay in simulation.
capture from the simulation
yes, i'm using quartus simulator. i'm new to designing in HDL and i don't know whether the results are correct. because in the examples i looked up, the output pulse (sync_clk) toggles as the input signal (sign_in) goes up. like in this one
Both results are correct, they just represent different types of simulation. Please consider that most of delay shown in the timing simulation is actually IO delay, which is large compared to internal logic cell delay.