[SOLVED] Rising Edge Detector Synchronization Problem

[hsnhsyn1]

hello, i designed an edge detector in verilog. it's RTL seems correct, but in simulation the output pulse is delayed. The examples on the internet, the pulse starts exactly with the rising edge of the clock signal. i used no delay in simulation.
capture from the simulation


and the code

module re_detector(Clk, sign_in, Sync_clk);

// input ports
input Clk, sign_in;
// output ports
output wire Sync_clk;
reg 	Q;
wire 	sign_in;

always@(posedge Clk)begin
	Q <= sign_in;
end
assign Sync_clk = sign_in & (~Q);
endmodule

 

[FvM]

What's your problem? The simulation is obviously a timing simulation, using realistic chip timing. The output like expectable from a real chip.

Apparently you are using Altera QSIM which does a gate level timing simulation.

 

[hsnhsyn1]

yes, i'm using quartus simulator. i'm new to designing in HDL and i don't know whether the results are correct. because in the examples i looked up, the output pulse (sync_clk) toggles as the input signal (sign_in) goes up. like in this one

http://fpgacenter.com/examples/basic/edge_detector.php

 

[FvM]

Both results are correct, they just represent different types of simulation. Please consider that most of delay shown in the timing simulation is actually IO delay, which is large compared to internal logic cell delay.

 

[hsnhsyn1]

thank you for your help