ned_zeppelin
Newbie level 6
I need a pulse of 1 clk_fast cyle duration, whenver clk_slow has a rising edge, in order to make a time stamp (of sorts) in the clk_fast domain.
Clk_slow and clk_fast are phase-aligned and generated from the same source. Clk_fast may be anything from 2 to 32 times faster than clk_slow.
I have implemented a "rising edge detector" circuit to generate the pulse as follows:
It detects the clk_slow posedge with one clk_fast cycle delay (i.e. it generates the pulse at the clk_fast posedge after the one coinciding with the clk_slow posedge). This seems to work, but if anyone has a better solution or any comments, please let me know.
However, my main concern is that I am using clk_slow directly as "signal" (clk_char is used as "clk" btw).
I fear using clk_slow directly in the logic like this is a bad idea?
So what is the general solution to this, if it is in fact a problem?
Any help is appreciated.
Clk_slow and clk_fast are phase-aligned and generated from the same source. Clk_fast may be anything from 2 to 32 times faster than clk_slow.
I have implemented a "rising edge detector" circuit to generate the pulse as follows:
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 module rising_edge_detect ( input wire clk, input wire signal, output reg pulse ); reg signal_prev; always @ (posedge clk) begin signal_prev <= signal; pulse <= signal & ~signal_prev; end endmodule
It detects the clk_slow posedge with one clk_fast cycle delay (i.e. it generates the pulse at the clk_fast posedge after the one coinciding with the clk_slow posedge). This seems to work, but if anyone has a better solution or any comments, please let me know.
However, my main concern is that I am using clk_slow directly as "signal" (clk_char is used as "clk" btw).
I fear using clk_slow directly in the logic like this is a bad idea?
So what is the general solution to this, if it is in fact a problem?
Any help is appreciated.
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