RF transistor layout question

[mohamedabouzied]

mos transistor layout rf performance

how about the layout of the RF nmos and pmos transistors?

does the RF transistor layout differs from the normal transistor layout?

so, can i use the model of the RF model in high frequency but at layout, i put the layout of the normal transistor?

and does this affect LVS stage after extraction?

thanx
mohamedabouzied

 

[khouly]

rf transistor layout

in RF transistor layout , u need to be carefull about the model , most the RF models specify how may gate contacts "single or double" ,

the body tie in RF NMOS is imprtant , it should be taken care

most of the new design kits should provide examples of the RF NMOS and PMOS transistors

khouly

 

[mohamedabouzied]

rf layout lvs

thanx
but i mean in my PDK there is an RF model "spectre model" for the nmos transistor
but when i come to layout, no layout available.
so, i gussed that the model is only a circuit model" a spice model" for the transistor at RF operation

but it is a normal transistor so, at layout i can use the layout of the normal transistor

am i right?

thanx again for replay
mohamedabouzied

 

[drabos]

layout for rf

maybe your design kit is not a full version, you should have a layout for the RF transistor... it may happen...

If you use the normal transistors in the layout, you should simulate with the model of the normal transistors

 

[khouly]

rf layout

no , there must be some examples to tell u how to layut the RF transistor ,
at least in the technology document , but sure it will look like ordinary transistor

khouly

 

[mohamedabouzied]

rf models

u khouly says no for me or for drabos?

and u drabos:
my design is a VCO working at 2.4GHz, so i must do simulations with RF models.

i do design under cadence and my pdk is: AMS Hit Kit 0.35

thanx for your repalys
mohamedabouzied

 

[khouly]

transistor layout

i say fr , u , if u check , in the process file , u will see how to make a layout of RF transistor

i mean , it will tell how , howmany gate fingers , this model is usful for , and is gate fingers , connetcted from one side or not , with these guide lines , u will draw a ordinary MOS , tansistor

but it will be compatible with this model

thanks

khouly

 

[mohamedabouzied]

in the ordinary transistor,
there iis a PCELL which generates the layout of it automatically
its parameters are W, L, number of gates
so i will use the ordinary transistor to generate its pcell layout.

but my simulations before layout will be with the RF model

mohamedabouzied

 

[khouly]

good , but take care for gate contacts

khouly

 

[mohamedabouzied]

u mean gate fingers
or what?
mohamedabouzied

 

[khouly]

there are 2 ways to connect gate fingers , and this affect the gate resistance
i know that the model of AMS , support single side gate contact , it means the fingers are connected from single side

khouly

 

[mohamedabouzied]

does the exraction step after layout depends on the spice model or just extracts what is seen with the extractor?
and when i do simulations on that extracted circuit, how does the simulator know that that transistor was an RF transistor?

mohamedabouzied

 

[khouly]

i think , u wiill specify , it to the simulator , the extactor , will get as transistor , and u will specify the model to be used

also try to get the new PDK , which is HITKIT 3.7 , i think it have new options , and it may make life much easier to u , also try to read process docuument files about process paramters , and spice models

khouly

 

[mohamedabouzied]

unfortunatly, i can't since i have this PDK with license.

thanx a lot.

and i have another question:
about my VCO i should match its output for maximum power transfer
i measured its output impedence, and i put a matching load Zload = Zout*
but when i did that, no output from VCO and the oscillation is dead.

why does this happened?


mohamedabouzied

Added after 2 minutes:

and my pdk is:

AMS hitkit-3.70

but still the life is hard

mohamedabouzied

 

[khouly]

don't match the Z out of the VCO , the VCO should be buffered "this is very imprtant for the VCO , then this buffer should drive the load or the MIxer

khouly

 

[drabos]

i will take a look at on AMS documents (now I don't have permission, now I work with other technology)
But there are some design kit which has RF MOS layout instance, but anyway believe in Khouly..he is more experienced in RF field.

I guess now there is also AMS 3.71, maybe it is better

Once I met with an AMS design kit, where I had the models for the high voltage transistors, but I didn't have layout instance for them (and they were in the category called don't use). I was thinking on that.

 

[jecyhale]

how about the layout of the RF nmos and pmos transistors?

does the RF transistor layout differs from the normal transistor layout?

so, can i use the model of the RF model in high frequency but at layout, i put the layout of the normal transistor?

and does this affect LVS stage after extraction?

thanx
mohamedabouzied

The model of RF is very improtant. because it will impact you performance especially in high frequency. Usually, we use RF p-cell to get the nmos and pmos.
but you will decide the size and the finger number.

So you should use the RF layout with RF model.