Hello.
I design, compile and make testbenchs to my VHDL project without using Quartus (I use a script that runs ModelSim command lines), so I don't use analysis or synthesis.
I don't know if it is that simple, but how can I estimate the resource usage for a design? It is kinda big, with 1000 or so lines, uses fixed-point arithmetics, many mathematics and other stuff.
Also, can I estimate the speed (in clock cycles, or maybe even time) that the design would execute, without actually running it? For example, for a 1 MHz clock, it would execute in [x] minutes.
If it matters, it's a project to process video and extract some features from the frames (calculate numbers, basically).
Thanks.