Reset Value using a parameter

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stanford

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Let's say that I have a data[WIDTH-1:0]. I want to use a parameter in RTL to provide the reset value for this data.

Code:
parameter RESET_VALUE = 5;
logic [WIDTH-1:0] data;

always_ff @(posedge clk)
  if (~reset)
    data <= WIDTH'd (RESET_VALUE);
  else
    ....

How do I make this work syntax wise? Is it even possible?

Thanks!
 


this is one of the few things I really like about system verilog, this problem went away completely.

in verilog, I believe you can use the concatenation operator {} to bypass this. you can use ifdefs too, but they are not as nice as parameters
 

I am using systemverilog, and it does not work. Syntax is not correct. Does anyone know how to fix it?
 
Last edited:

I am using systemverilog, and it does not work. Syntax is not correct. Does anyone know how to fix it?

I don't have a simulator to test right now, but I am pretty sure this is valid svlog code:

Code:
logic [999:0] myvar;

always (*) begin
    myvar = 'd0;
end
 

There's no need to size the parameter. Verilog/SystemVerilog always pads 0's implicitly.
Code:
parameter RESET_VALUE = 5;
logic [WIDTH-1:0] data;

always_ff @(posedge clk)
  if (~reset)
    data <=RESET_VALUE;
  else
    ....
 

There's no need to size the parameter. Verilog/SystemVerilog always pads 0's implicitly.
Code:
parameter RESET_VALUE = 5;
logic [WIDTH-1:0] data;

always_ff @(posedge clk)
  if (~reset)
    data <=RESET_VALUE;
  else
    ....

are you sure about verilog? integer constants are treated as 32 bit integers, as far as I remember. so in your example, if data has more than 32 elements, only some would be resetable.
 

I'm sure. Verilog (and thus SystemVerilos) implicitly extends or truncates the width of the RHS of a procedural assignment to match the LHS.
 

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