Apr 4, 2020 #1 S stanford Full Member level 2 Joined Feb 16, 2014 Messages 132 Helped 4 Reputation 8 Reaction score 6 Trophy points 1,298 Activity points 2,223 Let's say that I have a data[WIDTH-1:0]. I want to use a parameter in RTL to provide the reset value for this data. Code: parameter RESET_VALUE = 5; logic [WIDTH-1:0] data; always_ff @(posedge clk) if (~reset) data <= WIDTH'd (RESET_VALUE); else .... How do I make this work syntax wise? Is it even possible? Thanks!
Let's say that I have a data[WIDTH-1:0]. I want to use a parameter in RTL to provide the reset value for this data. Code: parameter RESET_VALUE = 5; logic [WIDTH-1:0] data; always_ff @(posedge clk) if (~reset) data <= WIDTH'd (RESET_VALUE); else .... How do I make this work syntax wise? Is it even possible? Thanks!
Apr 4, 2020 #2 T ThisIsNotSam Advanced Member level 5 Joined Apr 6, 2016 Messages 2,548 Helped 397 Reputation 794 Reaction score 463 Trophy points 1,363 Activity points 14,760 stanford said: Let's say that I have a data[WIDTH-1:0]. I want to use a parameter in RTL to provide the reset value for this data. Code: parameter RESET_VALUE = 5; logic [WIDTH-1:0] data; always_ff @(posedge clk) if (~reset) data <= WIDTH'd (RESET_VALUE); else .... How do I make this work syntax wise? Is it even possible? Thanks! Click to expand... this is one of the few things I really like about system verilog, this problem went away completely. in verilog, I believe you can use the concatenation operator {} to bypass this. you can use ifdefs too, but they are not as nice as parameters
stanford said: Let's say that I have a data[WIDTH-1:0]. I want to use a parameter in RTL to provide the reset value for this data. Code: parameter RESET_VALUE = 5; logic [WIDTH-1:0] data; always_ff @(posedge clk) if (~reset) data <= WIDTH'd (RESET_VALUE); else .... How do I make this work syntax wise? Is it even possible? Thanks! Click to expand... this is one of the few things I really like about system verilog, this problem went away completely. in verilog, I believe you can use the concatenation operator {} to bypass this. you can use ifdefs too, but they are not as nice as parameters
Apr 4, 2020 #3 S stanford Full Member level 2 Joined Feb 16, 2014 Messages 132 Helped 4 Reputation 8 Reaction score 6 Trophy points 1,298 Activity points 2,223 I am using systemverilog, and it does not work. Syntax is not correct. Does anyone know how to fix it? Last edited: Apr 4, 2020
I am using systemverilog, and it does not work. Syntax is not correct. Does anyone know how to fix it?
Apr 4, 2020 #4 T ThisIsNotSam Advanced Member level 5 Joined Apr 6, 2016 Messages 2,548 Helped 397 Reputation 794 Reaction score 463 Trophy points 1,363 Activity points 14,760 stanford said: I am using systemverilog, and it does not work. Syntax is not correct. Does anyone know how to fix it? Click to expand... I don't have a simulator to test right now, but I am pretty sure this is valid svlog code: Code: logic [999:0] myvar; always (*) begin myvar = 'd0; end
stanford said: I am using systemverilog, and it does not work. Syntax is not correct. Does anyone know how to fix it? Click to expand... I don't have a simulator to test right now, but I am pretty sure this is valid svlog code: Code: logic [999:0] myvar; always (*) begin myvar = 'd0; end
Apr 5, 2020 #5 D dave_59 Advanced Member level 3 Joined Dec 15, 2011 Messages 838 Helped 365 Reputation 734 Reaction score 360 Trophy points 1,353 Location Fremont, CA, USA Activity points 7,365 There's no need to size the parameter. Verilog/SystemVerilog always pads 0's implicitly. Code: parameter RESET_VALUE = 5; logic [WIDTH-1:0] data; always_ff @(posedge clk) if (~reset) data <=RESET_VALUE; else ....
There's no need to size the parameter. Verilog/SystemVerilog always pads 0's implicitly. Code: parameter RESET_VALUE = 5; logic [WIDTH-1:0] data; always_ff @(posedge clk) if (~reset) data <=RESET_VALUE; else ....
Apr 5, 2020 #6 T ThisIsNotSam Advanced Member level 5 Joined Apr 6, 2016 Messages 2,548 Helped 397 Reputation 794 Reaction score 463 Trophy points 1,363 Activity points 14,760 dave_59 said: There's no need to size the parameter. Verilog/SystemVerilog always pads 0's implicitly. Code: parameter RESET_VALUE = 5; logic [WIDTH-1:0] data; always_ff @(posedge clk) if (~reset) data <=RESET_VALUE; else .... Click to expand... are you sure about verilog? integer constants are treated as 32 bit integers, as far as I remember. so in your example, if data has more than 32 elements, only some would be resetable.
dave_59 said: There's no need to size the parameter. Verilog/SystemVerilog always pads 0's implicitly. Code: parameter RESET_VALUE = 5; logic [WIDTH-1:0] data; always_ff @(posedge clk) if (~reset) data <=RESET_VALUE; else .... Click to expand... are you sure about verilog? integer constants are treated as 32 bit integers, as far as I remember. so in your example, if data has more than 32 elements, only some would be resetable.
Apr 5, 2020 #7 D dave_59 Advanced Member level 3 Joined Dec 15, 2011 Messages 838 Helped 365 Reputation 734 Reaction score 360 Trophy points 1,353 Location Fremont, CA, USA Activity points 7,365 I'm sure. Verilog (and thus SystemVerilos) implicitly extends or truncates the width of the RHS of a procedural assignment to match the LHS.
I'm sure. Verilog (and thus SystemVerilos) implicitly extends or truncates the width of the RHS of a procedural assignment to match the LHS.