if the resst is synchronousely desserted .. i.e. it has to be synchronous to the clock edge when desserted .. this means that you need to either synchronize the first clock edge in both clock domains .. or have 2 seperate resets, one for each domain .. I also believe that you can have one global reset and a derived one ..
For the problem of asynchronous assertion and synchronous deassertion, there is an excellent paper by Cliff Cummings. It describes precisely this problem and proposes a solution to it. It is located at:
The above paper is very useful.
Make sure to cascade synchronize both resets as described.
it depends on your system requirements which cascade stage should come first (clk A or B)