[Req] Testbench by using system verilog with ModelSim

[elektrom]

Can you give me an example?

 

[wufengbo]

I think ModelSim don't support systemverilog fully.

 

[elektrom]

I saw from its datasheet that systemverilog 3.0 is supported, not 3.1 which is use for making test bench. Is it correct?

 

[nagraj]

I saw from its datasheet that systemverilog 3.0 is supported, not 3.1 which is use for making test bench. Is it correct?

Yes most of systemverilog 3.1 are used for verification

 

[Arnold]

you need to wait modelsim 6.1, I think

 

[Kulprashant]

hi,

i think modelsim 6.0 will support
systemverilog.please try to verify the dataheet

with regards,
kul.

 

[nand_gates]

Yes modelsim 6.0 supports SystemVerilog!
you can check running following examples...
**broken link removed**