I think synopsys tetramax and mentor fastscan is developed for test but not for verification. So I feel a good auto generator is not exist until now.
activehdl and other tools only can generate the framework of testbench. The test pattern is developed only by yourself.
I fell men*or's HDL designer series is one good design tools and also it is one good testbench generator. Then use m/o/d/e/l/s/i/m to simulate with the fpga vender's tool