Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Req: Post Synthesis Simulation tools

Status
Not open for further replies.

PigiPigi

Member level 2
Member level 2
Joined
May 1, 2002
Messages
43
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
271
Hi all,
I need a good post synthesis simulation tool for fpga designing. I also need a good test generator, but i don't know what is the best.
 

reky

Newbie level 1
Newbie level 1
Joined
Oct 2, 2001
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
8
Hi

FPGA synthsis tool is depend on what's fpga you want to use

Altera-->MaxplusII , QuartusII

Xilinx-->Foundation,
 

lipton

Member level 2
Member level 2
Joined
Jul 14, 2002
Messages
46
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
244
Re: Hi

reky said:
FPGA synthsis tool is depend on what's fpga you want to use

@ltera-->MaxplusII , QuartusII

Xilinx-->Foundation,

The request was for post-synthesis(gate level) simulation tool. Usually it's the same simulator used for RTL. If you are an Aldec fan, try Riviera.
 

CatKing

Full Member level 3
Full Member level 3
Joined
Jun 5, 2001
Messages
157
Helped
3
Reputation
6
Reaction score
2
Trophy points
1,298
Activity points
1,137
You can use any HDL sim tools do this job. But you have proper sim lib of the primitive cells first.
 

ccljpeg

Junior Member level 3
Junior Member level 3
Joined
Dec 8, 2001
Messages
26
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
138
xilinx can use modelsim and xilinx verilog lib , and get very accurate
timing
 

PigiPigi

Member level 2
Member level 2
Joined
May 1, 2002
Messages
43
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
271
And a good test generator?
 

linuxluo

Full Member level 6
Full Member level 6
Joined
Jul 26, 2002
Messages
331
Helped
7
Reputation
14
Reaction score
3
Trophy points
1,298
Activity points
2,514
I think synopsys tetramax and mentor fastscan is developed for test but not for verification. So I feel a good auto generator is not exist until now.
activehdl and other tools only can generate the framework of testbench. The test pattern is developed only by yourself.
 

my_garden

Member level 4
Member level 4
Joined
Dec 14, 2001
Messages
79
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
664
I fell men*or's HDL designer series is one good design tools and also it is one good testbench generator. Then use m/o/d/e/l/s/i/m to simulate with the fpga vender's tool
 

sandusty

Member level 5
Member level 5
Joined
Apr 19, 2004
Messages
89
Helped
3
Reputation
6
Reaction score
1
Trophy points
1,288
Activity points
910
I don't understand your question.

Since you are using FPGA, why do you want to run post sim? Why don't you just use FPGA.

If you want to run post sim, why does FPGA for?
 

eexuke

Full Member level 4
Full Member level 4
Joined
Mar 25, 2004
Messages
196
Helped
10
Reputation
20
Reaction score
3
Trophy points
1,298
Activity points
1,934
I suggest Modelsim. But post FPGA synthesis sim make little sense
 

Zerox100

Full Member level 6
Full Member level 6
Joined
Mar 1, 2003
Messages
327
Helped
21
Reputation
42
Reaction score
10
Trophy points
1,298
Activity points
2,595
Re: Hi

lipton said:
reky said:
FPGA synthsis tool is depend on what's fpga you want to use

@ltera-->MaxplusII , QuartusII

Xilinx-->Foundation,

The request was for post-synthesis(gate level) simulation tool. Usually it's the same simulator used for RTL. If you are an Aldec fan, try Riviera.

Why riveria? Why not ahdl?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top