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Req: Post Synthesis Simulation tools

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PigiPigi

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Hi all,
I need a good post synthesis simulation tool for fpga designing. I also need a good test generator, but i don't know what is the best.
 

reky

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Hi

FPGA synthsis tool is depend on what's fpga you want to use

Altera-->MaxplusII , QuartusII

Xilinx-->Foundation,
 

lipton

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Re: Hi

reky said:
FPGA synthsis tool is depend on what's fpga you want to use

@ltera-->MaxplusII , QuartusII

Xilinx-->Foundation,
The request was for post-synthesis(gate level) simulation tool. Usually it's the same simulator used for RTL. If you are an Aldec fan, try Riviera.
 

CatKing

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You can use any HDL sim tools do this job. But you have proper sim lib of the primitive cells first.
 

ccljpeg

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xilinx can use modelsim and xilinx verilog lib , and get very accurate
timing
 

PigiPigi

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And a good test generator?
 

linuxluo

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I think synopsys tetramax and mentor fastscan is developed for test but not for verification. So I feel a good auto generator is not exist until now.
activehdl and other tools only can generate the framework of testbench. The test pattern is developed only by yourself.
 

my_garden

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I fell men*or's HDL designer series is one good design tools and also it is one good testbench generator. Then use m/o/d/e/l/s/i/m to simulate with the fpga vender's tool
 

sandusty

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I don't understand your question.

Since you are using FPGA, why do you want to run post sim? Why don't you just use FPGA.

If you want to run post sim, why does FPGA for?
 

eexuke

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I suggest Modelsim. But post FPGA synthesis sim make little sense
 

Zerox100

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Re: Hi

lipton said:
reky said:
FPGA synthsis tool is depend on what's fpga you want to use

@ltera-->MaxplusII , QuartusII

Xilinx-->Foundation,
The request was for post-synthesis(gate level) simulation tool. Usually it's the same simulator used for RTL. If you are an Aldec fan, try Riviera.
Why riveria? Why not ahdl?
 

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