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req... design of DIRECT DIGITAL SYNTHESIZER

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stay_in_chaos

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hi friends!!!


can anyone help me out in design of DIRECT DIGITAL
SYNTHESIS.

here i need to implement phase accumulator and rom
inside the cpld. the output of the cpld
is given to the dac.

the input to the phase accumulator is
1. the frequency word

2. input frequency.

the output of the phase accumulator is used to address
the rom.
the output of the rom is given to dac.
the dacs output is theoutput frequency.


before designing the block.. i need some
clarifications..

1.how to detemine the min output frequency?
2.wht should be the size of the memory ie, in other
words, how many no of samples it should accomodate.
3.wht shold be size of the frequency register?

i have seen some datasheets which suggests that the
bit size of the frequency register is
more than that of bit size of rom. why is it so?
finally i need to design the circuit. (there is no
requirements).

can anyone help me out in getting related docs and
even verilog code,..for the same

thankz in advance
:D
 

Renjith

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Hi,
Check out this link:
h**p://www.xilinx.com/ipcenter/catalog/logicore/docs/dds.pdf

This application note describes DDS IP core developed by xilinx.
 

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