Report detailed area in Design Compiler/ Cadence Innovus

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oAwad

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If I'm using Design Compiler + Cadenece Innovus to synthesis and place&route a structural design, how to report the area and percentage that each block (structure) takes from the total design area? I'd like to determine the area that each block consumes so that I optimize it first. Any info. how to do this in either tool would be helpful.
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you need to report area hierarchically, that's all. just use report_area without any arguments and it should give you the data you need.
 

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