Replicate the following VHDL into Verilog?

LearningSoMuch · Dec 25, 2017

How would I replicate this VHDL process into Verilog

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
adding : process(a, b, inaddress, out) is
        variable addm :unsigned(32 downto 0);
    begin
        addm := ('0' & a) + ('0' & b) + inaddress;
        out <= addm(31 downto 0);
 
        inout_t <= addm(32);
 
        backout <= (addm(31) and not a(31) and not b(31)) or (not out(31) and a(31) and b(31));
    end process;

I am kind of new to this so I was just confused on this part. If someone could please show me how this process in Verilog would look, that would be helpful.

dave_59 · Dec 25, 2017

Code Verilog - [expand]
1
2
3
4
5
6
7
always @(*) begin : adding
    reg [32:0] adds;
    addm := a + b + inaddress;
       out        <= addm[31:0];
       inout_t  <= addm[32];
       backout <= (addm[31] && ! a[31] && !b[31]) || (! out[31] && a[31] && b[31]);
    end

ThisIsNotSam · Dec 26, 2017

The solution above should use blocking assignments for combinational logic.

Replicate the following VHDL into Verilog?

LearningSoMuch

Newbie level 2

dave_59

Advanced Member level 3

LearningSoMuch

ThisIsNotSam

Advanced Member level 5

Similar threads

Replicate the following VHDL into Verilog?

LearningSoMuch

Newbie level 2

dave_59

Advanced Member level 3

ThisIsNotSam

Advanced Member level 5

Similar threads

Privacy & Transparency

Privacy & Transparency