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Removing set up and hold violaions at RTL level

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Full Member level 3
Dec 10, 2014
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I know about fixing set up and hold violations in the PnR stages. Suppose my initial netlist itself has set up and hold violations. Can I remove them in RTL coding level?? In other words, how can I write an RTL code without set up and hold violations? Is there any specific methods for writing an RTL code with minimum set up and hold issues? or should we write the code according to our logic and check for the violations?

Hi biju4u90,
Pay attention to the logic level of big combitional logic can reduce set up violation. Hold violation is easy to fixed in PR stages.

While writing the RTL code, we won't be aware of the combinational blocks in the design, right? We will be simply writing the logic to be implemented and we won't be aware how the logic will be implemented. The implementation is done by the tool. Before generating the schematic of the design or before synthesising how can we pay attention to the combinational logic to reduce set up violation? Could there be any coding practice to take care or some other methods?

About hold violation, yeah... I can fix it easily in the PnR stage by adding delays. But suppose the hold violation in my initial netlist is too high. What is the right practice then?? Should I go to the PnR stage to fix it by adding too much delay elements or will I be able to rectify it by modifying my RTL?

While writing the RTL code, we won't be aware of the combinational blocks in the design, right?
Yes and no.

No, because you won't be aware of the exact implementation, e.g. how many LUTs need are cascaded. You see it indirectly by looking timing analysis results or directly by reviewing gate level net lists.

Yes, because a designer should have at least an idea how many levels of combinational logic are involved with certain RTL constructs, e.g. an arithmetic expression or be able to roughly estimate the maximal operation frequency of a n-bit counter implemented in a specific technology.
Is it fine to completely forget about hold issues in the RTL coding stage and think about them only in the PnR flow??

Yes, you can completely ignore hold at RTL coding level, as it is completely related to skew and balancing the clocks.

There is no specific way to reduce setup/hold when doing RTL coding. It is possible with experienced engineers who work on the same module, design, or block for many projects, and he knows well how RTL code can impact to the timing.

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