Hi,
Its always better , if could be done, to identify why they are at all appearing and what is the exact source of the error. Then definitely u can remove it by taking care of the source of errors.
In general:
(1) Offset Error:
It may come from common mode mismatch and/or total voltage level mismatch of in intra/inter block levels of the ADC. To explain, say , there is a small voltage level shift between ur THA out put and next block. Suppose ur THA should give Vos ~ 1V to 2V for the proper input voltage. But for some reason it shifts from 1.1V to 2.1V. Then this 0.1V will appear as offset of the ADC , if not compensated after wards.
To take care of this thing, you may ADD/Subtract, i.e. , shift the ADC output voltage in digital domain. Or u may have tunable reference voltages such that this 0.1V could be adjusted. There may be some other options which the designer could say better. This is, once again, dependent on architecture and block level realisation and also circuits followed.
In simulation level: You may adjust as needed. AT post-layoyt simulation level u may have to back annote and correct it. After fabrication, its tough of some options are not kept open like said above or else.
(2) Gain Error:
Almost the same idea applies here. Say ur THA is giving a gin of 0.9 instead of 1.0. This will give a gian error of the ADC. U may do something like the above: Tunable reference points; gain adjustment option to the THA etc.
Please note that I have taken THA as the source of error for both of the cases above. It is not necessarily the case. So better to identify the source of the error. If it cannot be done; for gain error ; u may compensate with a block with gain ~ 1/(errored_gain) of the ADC before u feed it to the ADC.
sankudey