I am making tests with a ring oscillator (RO) in ADEL Cadence. But when I increase the size of the RO from 13 to 121 stages there are glitches in the output signal of the RO (image attached). How can I make the output frequency of the RO a stable signal? Because this is also generating errors for aging simulation in ADEL.
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Those aren't "glitches". They are full scale, fully settled reswitch
(chatter). Moreover it appears repetitive.
Your RO should have one and only one cycle of a standing wave.
Stop the cycle and see whether you have sub-cycles within the
bit field. Like do you have
11111100000...0001111111111
or
11111101000...0001011111111
The latter problem maybe wants a better initialization or logic
that scrubs rogue singlet bits continuously.
It may be that, if you are current starving this RO trying to get
low frequency, you are forcing the stages to operate with so
little gain that there is a lot of local noise pickup, and (say)
the next stage's output switch bounces the predecessor's
input to reswitch it. Look at the input amplitudes, are they
well formed "digital" (as a non-starved RO would be, at that
stage count) or are they low amplitude centered around the
switchpoint, thus near zero noise margin?
Of course in an ideal simulation many coupling modes are absent.
Add interconnect C, or RLC, and you'll see some icky stuff I bet.
Consider getting your low frequency by fewer stages and
a post-divider (like your successful 13, and a /8 or /16 prescaler?)