[SOLVED] relation between pipelining and clock latency................................

[dipin]

hi,


in verilog coding is there any relation between clock latency and pipelining????

in a xilinx ip core if i choose maximum pipelining for 16 bit input latency is 9 and for optimal pipelining latency is 6 and with no
piplining latency is 2.

i have used xilinx square root ip.

please give me some information.

thanks & regards

 

[TrickyDicky]

Pipelining is the insertion of registers to increase the latency. The reason we do this is to reduce the amount of logic between registers to improve the overall maximum clock frequency.

I not exactly sure of your question.

If you set the latency to 9, the output will come out 9 clocks after it is input.