regulator overshoot when power on

[zarric]

i'm design a on chip regulator for internal 5v supply, the input max. voltage is 40V.

i apply a pwl voltage source to simulation, when start up , volatege reference is not setted , and regulator output is has a large overshoot

who can help me how to elimilate it.

 

[pranam77]

Which devices are you using. Posting your schematic will be a worth thousand words. Cheers

 

[mdcui]

pay attention to the current loading of your regulator, sometimes, if current loading is not stable during power up, say, too small current, then the output voltage may fluctuate heavily, if your regulator is the traditional sample and feedback type.

Added after 1 minutes:

and to continue on this topic, when we design regulator, sometimes, we put a constant current dumping or controlled current dumping circuit under it, so that the dynamic of current supply range can be reduced, to help the stability of output voltage.

 

[dick_freebird]

The supply dV/dt is a significant input, and if you have a fast
edge and a poor high-frequency PSRR the loop has not much
chance of controlling the action.

You want to know what the real lower bound of supply risetime
is (at test and in application).

If there are problems because the reference has not started,
think about a suppression circuit that jams the regulator
powertrain to "off" until reference is up, and perhaps some
positive timeout afterward. This ought to ensure that you are
not seeing an extremely dynamic input supply.

If the reference also is the source of housekeeping bias, then
you may be trying to deal with the supply activity without
even being properly lit up. You might want to separate the
regulation reference, from the housekeeping or make it so
the housekeeping is "early-on" (perhaps crudely) and then
the bandgap-based one takes over when it's up on plane
for better regulation.