Regulated voltage simulation problem

[ehsantech]

Hello
Here is my circuit and output


but when I changed R1 from 100 ohm to 50ohm and I want to see more distortion it confused me with this output

1-why did distortion decrease?
2-why didn't distortion be present after 10ms?

 

[FvM]

There is no "distortion". It's instable regulator operation.

Not sure about it, but I guess the problem is that you have used an ideal capacitor (with zero ESR) in your simulation circuit. Classical voltage regulators aren't designed for stable operation with low ESR output capacitors. Place a series resistor modelling the capacitor ESR, e.g. 50 or 100mOhm.

 

[ehsantech]

Thank you dear FVM
could you tell me more about the reaction of ESR of capacitor in this circuit?how does it cause this problem?