What is the exact clocking scheme? it might be best to use a DCM as a zero-delay clock buffer. from there, you can choose to run the system on any phase-shifted clock. This method has the advantage that clock-to-out of the ADC, and input to Clk (of the system clock), and other delays are largely removed. This setup requires the ADC send an output clock to the FPGA.
it still might be useful to look at the DC switching datasheet to see what the setup/hold margins are for your chosen clock scheme.
It may still be worth using a DCM as zero-delay buffer in the system-sync case, as the input to global clock delay can be several nanoseconds.
In the end, the spartan should have IDDR registers. using these, you can select between rising/falling easily.