[SOLVED] register implementation by vhdl

[ahmadagha23]

hi
what is the vhdl code for implementing a 8bit register for virtex2 fpga?
thanks

 

[maestor]

...
:?

That question m8... lacks a lot of basic knowledge about VHDL or FPGA architecture. Ok, ok, I didn't know the answer when I started and we are all here to help

I think you should read a bit about VHDL and FPGA architectures before asking for any code, a code you can write yourself. There are very good books about these issues and they have been posted many times.

--maestor

 

[hoangthanhtung]

hi
what is the vhdl code for implementing a 8bit register for virtex2 fpga?
thanks

Many example can teach you how to implement a 8 bits or more register in this site or intenet. You can search by using google or you can read the taxt book "VHDL by examples". Good luck

 

[delay]

Is this a shift register p2s, p2p, s2s, s2p? or a simple register that sets certain bits e.g., version, NMI etc?

 

[eltonjohn]

rgistered logic on a FPGA is not a special construction on a Virtex or any other FPGA . You need to know the sematics on the synthesis language that you want to use .. In Vhdl there is a problem because it has to be IMPLIED the language itself being a general simulation language doesn't have special semantics .. But is up to the synthesis tool to recognize the implied registered construction . I did a post on that ,some time ago ..search ..search my friend ..

 

[ahmadagha23]

Hi dear friends my structure that I want to know its vhdl code is in the attached file plese look at it and send me its vhdl code,I have write its vhdl code but when I synthesize it by synplifypro its syntisized shematic is different.I will send you its vhdl code soon.please send me your vhdl source code for this shematic
yhanks

 

[ahmadagha23]

hi I ziped and attache you the schematic:

Do not add a new post shortly after your last post!!!
Edit last post instead!!!
Next time warning
/davorin

 

[ahmadagha23]

hi
what is the difference between latch and register?

 

[ramesh]

hi
what is the difference between latch and register?

Latch is level sensitive (input data is transparent to the output till the level is active and output holds this data when the level is inactive) . Register is edge sensitive (transfers the input data to the output on clock's either positive or negative edge).

 

[SphinX]

Salam,

In other words,

Latch and flipflop (the basic unit of registers) are type of bistable storage device.

The difference in the method used for changing their state as "Ramesh" explained.

Bye