[SOLVED] register coding for datapath

[zadulhuda]

can i get the coding vhdl register for 16 bit register to make datapath by using xilinx. Please help me.:smile:

 

[TrickyDicky]

what have you done so far?

 

[BlackHelicopter]

I have no idea what you're talking about, but in Xilinx's ISE go under Edit -> Language Templates -> Synthesis Constructs -> Coding Examples -> (I'm guessing you're looking for something either under 'Flip Flops' or 'Shift Registers'). Have a look and modify them as you see fit.

 

[zadulhuda]

what have you done so far?

i have done coding for 2-to-1 MUX, ALU and tri -state buffer.
This is my task: implement the datapath and design control words that add-up the following hexadecimal numbers:- $23,$AB,$79,$54 and $88 using the datapath.
Now, i have a problem whereas I not know what register cosing(vhdl) for 16 bit register in xilinx...can help me?

 

[TrickyDicky]

try looking at standard synchronous templates:

process(clk,reset)
begin
  if reset = '1' then 
    --async reset goes here
  elsif rising_edge(clk) then
    --sync stuff goes here
  end if;
end process;

 

[zadulhuda]

try looking at standard synchronous templates:

process(clk,reset)
begin
  if reset = '1' then 
    --async reset goes here
  elsif rising_edge(clk) then
    --sync stuff goes here
  end if;
end process;

I want to ask you, if in my register, there are load, clear,clock and 1 input from the ALU that rename as F, can I uses this coding?




refer to above picture, the register has 4 input which are load, clear, clock and F and D as the output, am I correct? can I uses this coding?

 

[TrickyDicky]

you can use whatever coding you like. I suggest reading the altera coding guidelines
https://www.xilinx.com/support/documentation/white_papers/wp231.pdf

 

[RMTREDSTON]

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