Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Regarding Universal Pheriperal Bus evolution

Status
Not open for further replies.
K

kotta

Junior Member level 2
Joined
Nov 21, 2006
Messages
22
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,439
1. Master
1. Read related Inputs
1. rd_clk
2. rd_addr_ready
3. rd_data_valid
4. rd_data
5. rd_response (Kinda rd_strobe)
2. Read related Outputs
1. rd_addr
2. rd_addr_valid
3. rd_transaction_id
3. Write related Inputs
1. wr_clk
2. wr_addr_ready
3. wr_data_ready
4. wr_response
4. Write related outputs
1. wr_addr
2. wr_data
3. wr_addr_valid
4. wr_data_valid
5. wr_strobe
6. wr_transaction_id

Will all the above common port list will not be sufficient to have a Unified Peripheral Bus Protocol.

I guess almost all existing bus protocols resembles the same port list kind.

Then why cant be such Unified Peripheral Bus Protocol our Chip Industry follow, to avoid SOC inegration hazzles.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top