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A high speed UART can be appropriate as a simple interface between digital systems, e.g. using a LVDS IO standard. For the receiver, you'll need a sufficient oversampling ratio. I'm e.g. using a 40 MBps UART with factor eight oversampling. A suitable system clock is needed too.
When representing standard UART frequencies, there may be a problem to generate the right baud rates. But in FPGA design, you have all options like unusual overampling ratios and fractional frequency dividers. I designed e.g. a 115 kbps UART running from a low 6 MHz clock, using a factor 13 oversampling ratio.